Academic snapshot
Marks: 7.0 CGPA; 60% in 10th/12th commonly cited
Degree: B.Tech/M.Tech ECE/EEE/E&I; CSE for Embedded
Backlogs: None active
Year: Final year / intern as posted
Texas Instruments Placement Papers 2026
Texas Instruments designs analog chips and embedded processors used in electronics worldwide. Its main India hub for students is in Bengaluru, near the Bagmane Tech Park area. TI recruits campus graduates for analog design, embedded software, and semiconductor engineering roles.
Explore: Online Assessment · Download PDF · Placement Process · Interview Experience · Preparation Guide · Certifications & Career
Texas Instruments eligibility & CGPA (2026)
TI does not publish one forever cutoff for every India drive. Campus JDs at IITs, NITs, BITS, and select private colleges still cluster around the same floor. Treat numbers below as candidate-reported as of August 2026.
Who this hub is for
- For: ECE / EEE / Instrumentation students targeting Analog Engineer, Digital Engineer, Applications, and CSE students targeting Embedded Software. Intern and FTE campus loops share the same HirePro flavour.
- Not the same track: Experienced analog layout or field-apps roles with years of Cadence. This hub is the campus filter: aptitude + profile MCQs + project interview.
- Engineering Physics / MnC: Open on some intern lists (IIT Guwahati cited Physics for several roles; Embedded added CSE/MnC). Read the cell mail.
Degree, marks, backlogs
- Degree: B.Tech or M.Tech in ECE, EEE, Electronics & Instrumentation, or a closely related electronics stream. CSE for Embedded/Software.
- Graduation: 7.0 CGPA or about 60% aggregate is the line IIT Kharagpur / IIT Guwahati write-ups keep repeating.
- Class 10 and 12: 60% or equivalent on many FACE Prep / campus summaries. Keep marksheets.
- Backlogs: None active at application. Cleared-but-historical backlogs are treated differently by drive; safest is zero.
- Year: Final-year for campus FTE; intern drives target pre-final as posted. Off-campus careers.ti.com often wants grads within about a year.
Who usually fits and who struggles
Good fit: You can sketch a first-order RC transient without writing a differential equation. You can walk an ADC project from sampling capacitor to comparator kickback. Or, for Embedded, you can write endian-aware C and talk cache lines. You picked two profiles and ignored the third.
Harder path: You only watched Razavi playlists and never solved a numerical. You guess on aptitude (negative marking). You claim Analog interest but cannot open your own lab report. A 9.0 with shallow projects loses to a 7.2 who lived in the ADC schematic.
Branch myth: CSE is not auto-rejected. It is usually not on Analog/Digital. Do not spend August on current mirrors if your only open role is Embedded. Conversely, ECE is not blocked from Embedded if C is real.
On-campus vs careers.ti.com
| Route | What usually changes | What stays the same |
|---|---|---|
| Campus (IIT/NIT/BITS/select) | CDC list, HirePro slot, two-profile cap | Fundamentals bar |
| careers.ti.com | Year-round student/entry roles | Same families: Analog, Digital, Embedded, Apps |
| Referral | Visibility | You still sit the test |
Campus gives a batch window. Careers gives more attempts and a denser pool. Technical content does not get easier off-campus.
CGPA: printed floor vs selected cluster
Is 7.0 enough? It is the printed floor on multiple 2024-2025 IIT accounts. Selected analog/digital candidates are often above it and project-strong. TI weighs profile technicals + project defence after the resume screen.
| Hiring route | Typical filter (reports) | What actually filters you |
|---|---|---|
| On-campus | 7.0 CGPA; 60% in 10th/12th | Cell list + HirePro + interviews |
| Off-campus | Same printed baseline; fewer seats | Resume + OA + role fit |
| Selected cluster | Often 7.5+ with real labs | Project depth in the hour |
Selection chances by CGPA band
| CGPA range | Rough chances | Reality check |
|---|---|---|
| Below 7.0 | Low on-campus | Careers only if the JD allows it |
| 7.0-7.4 | Medium | Aptitude accuracy + one strong profile |
| 7.5-8.5 | High | Common shortlisted band with labs |
| Above 8.5 | Very high if projects hold | CGPA never explains a current mirror |
Skills they actually filter
Primary: Profile fundamentals + project depth
Languages: C, C++, Python; Verilog (Digital)
Exam filter: HirePro TI Online Test
TI is a core semiconductor hire. Clearing 7.0 only gets you a HirePro seat. Treat aptitude accuracy as the first cut, profile MCQs as the shortlist, and project defence as the offer conversation.
Texas Instruments placement papers - last few years
Download 2026 Texas Instruments placement papers
2026 in detail
2025 placement papers
2024 placement papers
Previous year question papers
Comments & Suggestions
What Texas Instruments previous year papers actually train
TI does not publish a permanent official paper. “Previous year papers” on this site are pattern trainers for HirePro aptitude, Analog/Digital/Embedded MCQs, and interview-style C or circuit prompts. They are not leaked live items.
| Round (typical) | What to practice |
|---|---|
| Aptitude (common) | Arithmetic speed with negative marking |
| Analog technical | RC, op-amps, MOS, current mirrors |
| Digital technical | Boolean, FSM, timing, Verilog basics |
| Embedded technical | C/pointers, bits, OS, light DSA |
| Interviews | Project depth, not contest graphs |
Think of papers as simulators for a two-section clock. TI reuses families (first-order RC, setup/hold, pointer aliasing) more than exact clones. If you can finish a 2024 aptitude block without guessing, a 2026 HirePro will feel familiar even when the MOSFET trap is new.
Themes that keep repeating (2024-2026)
- HirePro shape (IIT Guwahati intern account): 20 aptitude (30 min) + 20 per role (45 min each). Shortlists split by profile (example counts: Analog 5, Digital 14, Embedded 9, Signal Processing 5).
- IIT Kharagpur 2024 (Arpan Deb, Analog): Common aptitude then Analog + Digital technicals. Interview: first/second-order RC without differential equations, poles/zeros, current mirrors, SAR ADC sampling capacitance, Flash ADC gray encoding, then 30-40 minutes on ADC projects (power, comparator, redundancy). Offer in Analog before the Digital interview.
- IIT Kharagpur 2025 (Satya Sai Kommana): Analog VLSI Engineer. Written + one technical + HR (some peers had two technicals). CGPA 7.0. Core subjects beat PORs.
- Software on-campus (GFG): 20 aptitude (30 min) + 10 technical MCQs (45 min), no coding in written. Interview jumped to endianness C, cache coherence, aligned malloc. 2 of ~24 software shortlists selected.
- 2026 prep expectation: Same profile split. No rumour of a sudden LeetCode analog paper. Keep negative-marking discipline and one project you can open cold.
How to use one paper set in a single sitting
- Timed: 20-30 min aptitude (no guessing) → 30-45 min one profile technical.
- Untimed review: rewrite every question you marked “maybe.” Those are the ones HirePro punishes.
- Map misses to a theme (RC time constant, setup time,
char*aliasing). - Open the matching lab/project and explain it out loud for 10 minutes.
- Log one interview follow-up the MCQ reminded you of.
Related problems to practice
| Theme you saw in a set | What to drill next | Why TI asks it |
|---|---|---|
| RC transient / bode by inspection | Razavi/Neamen problem sets | Analog interview opener |
| Current mirror / MOSFET region | Small-signal limits | Analog MCQ + interview |
| FSM + Verilog NBA vs BA | Draw Moore machine, then code | Digital |
| Setup/hold | Timing diagram on paper | Digital |
| Pointers / endianness | Write swap and dump bytes | Embedded/Software |
| Aptitude PnC / time-work | Accuracy, not volume | Common section |
Texas Instruments hiring rounds in 2026
TI hires freshers through campus cells (IITs, NITs, BITS, select private colleges) and careers.ti.com. After eligibility, the shape is semiconductor-classic: a shared aptitude gate, a profile technical, then a long project interview.
Application methods
Campus recruitment
Primary path. PPT → HirePro → 1-2 technicals (Cisco Webex/screen-share on some intern drives) → HR. Bengaluru joining is the usual India story.
Online applications
careers.ti.com. Resume screen → OA invite → interviews. Useful if your campus missed TI.
Referrals
Help visibility. You still need aptitude accuracy and a project you can defend.
1. Eligibility / resume
7.0 CGPA, 10th/12th 60%, branch list, no active backlogs. Resume should scream one profile: ADC/op-amp labs for Analog, FSM/Verilog for Digital, C/OS projects for Embedded. A generic “interested in VLSI” line with a web-dev stack is a skip.
2. HirePro online test
| Section | Questions | Time | Notes |
|---|---|---|---|
| Aptitude (common) | ~14-20 | ~20-30 min | Negative marking reported. Arithmetic, time-work, probability, PnC, some logic/verbal. |
| Analog technical | ~20 | ~30-45 min | RC, op-amps, MOSFET regions, current mirrors. Second-year depth, tricky wrapping. |
| Digital technical | ~20 | ~30-45 min | Boolean, sequential, FSM, timing, architecture, sometimes Verilog. |
| Embedded Software | ~20 | ~30-45 min | DSA, C/C++ pointers, OOPs, OS, networks, DBMS, bits. |
Two-profile cap: Analog + Digital is a common pair. You do not get all three technical blocks on a typical invite.
Software-role variant (GFG): 20 aptitude (30 min) + 10 technical MCQs (45 min), no coding in written.
Pass habit: FACE Prep / KGP notes say ~11-12 correct out of ~20 on aptitude is often enough because guessing is expensive. Skip. Do not hero a 8-minute DI.
Deeper OA notes: Texas Instruments online assessment.
3. Technical interview (1-2 rounds, ~45-75 min each)
Many panels spend 20-40 minutes on CV/projects before core questions. Some start with 15-20 technicals and never open the CV (Utsav Agarwal analog intern note). Both happen.
Analog: RC by intuition (no DE if you can avoid it), poles/zeros, current mirrors, ADC sampling, comparator topology, power, redundancy algorithms. If you built an ADC, budget half the hour for it.
Digital: Concept choice allowed on some Webex intern panels. FSM end-to-end, setup/hold, Verilog blocking vs non-blocking, timing diagrams on a shared screen.
Embedded/Software: Endianness C, cache coherence, memory alignment, aligned malloc, bit manipulation, OS. Be ready to write/debug on a shared editor.
IIT Guwahati intern: Digital interview ~1h15 including your questions; results next day.
4. HR (~15-20 min)
Why TI?, career goals, free time, joining Bengaluru, intern vs FTE conversion. Several accounts say reaching HR means technical is largely cleared. Do not freeze on a simple “why semiconductors.”
| # | Round | Duration | What they check |
|---|---|---|---|
| 1 | HirePro OA | Aptitude + 1-2 profiles | Accuracy, fundamentals |
| 2 | Technical 1 | 45-75 min | Projects + core |
| 3 | Technical 2 (some) | 45-60 min | Deeper same profile |
| 4 | HR | 15-20 min | Fit, city, intent |
Timeline from application to offer
| Phase | Typical duration | Notes |
|---|---|---|
| CDC / apply | Days | Pick two profiles |
| HirePro | 1 slot | Separate timers per section |
| Interview | +1-3 days | Webex or on campus |
| HR | Same day or next | Often short |
| Result | 1-3 days | Intern IITG: next day |
| End to end | ~1-3 weeks on campus | Off-campus longer |
Profile cheat-sheet
| Profile | OA focus | Interview focus | Who should sit it |
|---|---|---|---|
| Analog | Circuits MCQs | RC, MOS, ADC projects | ECE/EE with labs |
| Digital | Logic + Verilog | FSM, timing | ECE/EE who like sequential |
| Embedded | C + OS MCQs | Pointers, cache, bits | ECE or CSE with C |
| Software (some) | Apt + short tech | Systems C | CSE with OS depth |
Aptitude: a clock that respects negative marks
| Minute | Move |
|---|---|
| 0-12 | Sure arithmetic (percentages, ratio, time-work) |
| 12-20 | Probability / PnC only if you see a clean path |
| 20-25 | Verbal/logic leftovers |
| Last 5 | Do not fill remaining bubbles |
Eleven confident ticks beat eighteen guesses. That is the whole sport.
Analog interview: RC without the DE
Interviewers like first-order and second-order intuition. Practice:
- Step response of RC: time constant, 63% point, what a bigger C does.
- Bode: pole from the same RC, decade/octave slope talk at a fresher level.
- “What if I add a series R?” before you write KCL.
If you reach for Laplace on every question, you will run out of time before the ADC project. Inspection first, equations when they ask.
Digital: FSM on paper in 10 minutes
- List inputs/outputs and states.
- Draw Moore or Mealy and say which.
- Write the transition table.
- Mention setup/hold on the clock edge that samples.
- If Verilog: non-blocking in sequential
always, blocking in combo.
That sequence is more useful than memorising 50 MCQs you will not see again.
Embedded: three C questions to write cold
- Swap two ints with pointers; then explain what breaks if they alias.
- Print bytes of an
intto show endianness. - Align an allocator:
(ptr + align-1) & ~(align-1)and why it matters for cache lines.
If you cannot write these without Stack Overflow, do not pick Embedded as your second profile “for backup.”
Documents and lab reports
Carry ID, resume, and the schematic or report for the project you listed. TI analog interviews go into sampling capacitance. If the number is only in a forgotten PDF, you will look unprepared. Software candidates: have a snippet of the C you claim.
Weekend mock that matches a HirePro day
Saturday morning: 25-minute aptitude with a no-guess rule. Score only the questions you would actually click.
Saturday afternoon: 40-minute Analog or Digital MCQ set, then 15 minutes teaching your project to a roommate.
Sunday: second profile if you are sitting two; otherwise Embedded C drills (endianness, aligned malloc, one bit-manipulation).
Two weekends of that beat a Razavi binge with zero timed aptitude.
Analog numerical habits that transfer
You do not need every Sedra/Smith chapter. You need inspection:
- Double C, double tau, half the pole frequency talk.
- MOSFET: name the region before you write gm. Saturation vs triode mistakes are the classic MCQ trap.
- Current mirror: what happens if the output node drops too low? (compliance)
- Op-amp: virtual short only if the loop is closed and the device is ideal enough. Say the assumption.
Write those four sentences from memory. If you cannot, the interview will feel like a viva you did not attend.
Digital timing in one diagram
Draw a clock, a flop, a combo cloud, and the next flop. Mark Tcq, Tpd, Tsetup, Thold. Then say, out loud, when the design fails setup vs hold. That diagram is worth more than 30 random Boolean MCQs. Verilog: non-blocking in clocked blocks, blocking in combo; if you mix them, say you know why that is a race.
Why TI (a 40-second version)
“I want to design circuits that ship in volume, not only simulate them once in a lab.” Analog/Digital at TI matches the projects I already stayed late for.” Swap Analog/Digital/Embedded for the profile you sat. Do not quote the company Wikipedia.
Intern vs FTE on the same HirePro
Intern and FTE often share the test. Interviews may be slightly shorter for intern. Conversion language is not automatic. If you want FTE, say so in HR and ask how conversion worked last year. Do not assume a summer intern letter is a 2027 joining date.
What “core” means for your calendar
TI analog prep does not stack cleanly with a LeetCode-only product-company plan. If you are also sitting Qualcomm/Intel software, keep C/OS as the overlap and schedule circuit problem sets as TI-specific hours. Trying to “do all core plus all DSA” in one week is how both papers go badly.
Night-before rule: no new Razavi chapter. Replay the project lecture once, sleep, carry the schematic print. If you sat two profiles, reread only the one you expect to interview for first; mixing Analog and Digital notes at 1 a.m. is how both go fuzzy.
Texas Instruments practice pages
Week-by-week plans live on the preparation guide, not here.
Online assessment
OA format, timing, and question types.
Coding questions
DSA patterns for OA and technical rounds.
Aptitude / mock quiz
Quant, logic, and timed mock quiz.
Interview experiences
Candidate stories and round notes.
HR interview questions
Common HR questions, sample answers, STAR tips.
Week-by-week prep
Study plan and round-by-round strategy.
Where your Texas Instruments prep time should go
If a Texas Instruments invite is 3-8 weeks out, treat this hub as the map and the linked practice pages as the drills. Do not reread eligibility ten times. Check the JD once, then spend hours on the filter that actually rejects people.
Typical fresher CTC chatter for Texas Instruments sits around ₹14-25 LPA (candidate-reported - confirm the letter). Languages students mention most often: Java, C++, Python, C. Pick one and stay with it in OA and interviews.
Eligibility reminder (from student reports): Campus reports commonly cite 7.0 CGPA (or ~60% aggregate) plus 60% in Class 10 and 12, no active backlogs. Degrees: B.Tech/M.Tech in ECE, EEE, Instrumentation, or related electronics streams. CSE/MnC often eligible for Embedded Software. Final-year and recent grads. Always verify careers.ti.com or your placement email.
What you are training for: Typical campus shape: HirePro online test (common aptitude, then profile-specific Analog/Digital/Embedded MCQs; at most two profiles) → 1-2 technical interviews (sometimes 1-3; project-heavy) → short HR. Core analog/digital roles usually have no coding in the written test. Software/Embedded written sections differ by drive. End-to-end often 1-3 weeks on campus.
Short version of the prep split: Pick at most two profiles. Aptitude: accuracy first because of negative marking. Analog: RC intuition, op-amps, MOSFET regions, current mirrors. Digital: Boolean, FSM, timing, Verilog. Embedded: C pointers, bits, OS/cache. Then defend every CV project to component level. Full plan: /texas-instruments/preparation-guide/.
A four-week plan that actually gets used
Week 1 - pattern, not vibes. Language fluency: rewrite 10 old solutions in one language until you stop hunting syntax. Open the Texas Instruments previous-year sets on this site and mark which sections ate your time. Write the timing on a sticky note. That number is more useful than a 200-problem LeetCode streak you never timed.
Week 2 - the steep filter. Most Texas Instruments drives fail people on the first timed paper or OA. Do three timed sits this week. After each one, log every miss in a two-column note: topic and why (slow, wrong formula, bad edge case, panic). The next sit should only add problems from that log.
Week 3 - talk tracks. Technical interviews at Texas Instruments usually want a clean project story, one or two CS fundamentals, and (if the process has it) a behavioral or values round. Write STAR stories on paper, not in your head. Practise “Why Texas Instruments?” with one concrete product, lab, or business line - not a slogan.
Week 4 - mocks and logistics. Sleep, id photocopies, and a dry run of the oa platform if the invite names one. If you still have energy, redo only the questions you failed in week 2.
Where the hours should go
| Slice | Share of weekly hours | What “done” looks like |
|---|---|---|
| Timed papers / OA | ~40% | You finish a Texas Instruments-style sit without guessing the clock |
| Coding / role technical | ~30% | You can explain a solution out loud in your chosen language |
| Fundamentals / domain | ~20% | You can teach one OS/DBMS/networks (or domain) topic to a friend |
| Stories + HR | ~10% | Two STAR stories and a specific Why-this-company answer |
If you only have 10 days, keep the same ratios and cut volume, not the timed sits.
Practice pages to open this week
- OA / assessment notes
- aptitude mock quiz
- coding question bank
- interview experiences
- HR question bank
- week-by-week guide
- previous year papers
- 2026 paper page
Use this hub for the Texas Instruments story (eligibility, rounds, salary). Use those pages for timed reps and interview notes.
Common ways students waste a month
- Collecting 12 Texas Instruments PDFs and never sitting one under a timer.
- Switching languages every weekend because a senior used a different one.
- Memorising HR answers before they can finish the OA.
- Ignoring the company-specific quirk on this page (unique round, exam name, or role band) and preparing like a generic service-company drive.
If you do one thing after reading this: schedule three timed Texas Instruments papers on three different days, then interview prep on the leftovers.
If you are starting from a service-company prep base
A TCS/Infosys aptitude deck still helps the quant/logic slice of many Texas Instruments papers, but do not assume the same cutoff culture. Read the process section on this page once, then swap in Texas Instruments-specific coding or domain drills from the nested banks. Shared prep is fine; shared assumptions about rounds are not.
10-day crash version
Days 1-3: one timed Texas Instruments paper each day plus error log. Days 4-6: only the topics you missed, plus 4-6 coding problems in one language. Days 7-8: project + STAR + Why Texas Instruments. Day 9: one more full mock. Day 10: light review and sleep. This is worse than four weeks, but it beats rereading notes the night before.
Texas Instruments compensation & benefits
Figures are candidate-reported India bands as of August 2026.
| Band | Typical CTC (reports) | Notes |
|---|---|---|
| Analog / Digital / Embedded FTE | ₹14-25 LPA | Bengaluru core campus band |
| Software-only campus | Overlaps lower-mid of that range | Confirm JD |
| Internships | Stipend, not CTC | Conversion is a separate letter |
Confirm base vs bonus vs joining city on the written offer. Treat ₹14-25 LPA as a reported band, not a guarantee for every profile.
Benefits students actually care about
- Health insurance
- Learning / internal analog-digital mentoring culture (shows up in Why TI answers)
- Bengaluru office norms (Bagmane-area hubs)
- Intern-to-FTE path on some campus programs
How to talk CTC in HR
Know the band. Ask city. Do not negotiate like a product-SWE blog in the first HR. Core semiconductor offers are already above typical services GET numbers; the filter is technical, not haggling.
Offer-stage discipline
- Read profile name (Analog Engineer vs Digital vs Embedded)
- Confirm intern vs FTE and conversion language
- Do not resign another offer until the letter lands
- Background check will match 10th/12th/CGPA
Recent Texas Instruments placement trends
- Profile-split HirePro is still the written shape. Two-profile cap remains the planning constraint.
- No coding on classic Analog/Digital written tests. Do not waste August on graphs if you are Analog-only.
- Project-first interviews are the 2024-2025 KGP pattern. Labs beat POR lists.
- 7.0 CGPA is still the cited campus floor. 10th/12th 60% still appears in summaries.
- Bengaluru remains the India engineering centre students name.
- Treat ₹14-25 LPA as the reported FTE band, not a services 5 L number.
Net for 2026: pick two profiles, protect aptitude accuracy, and rehearse one project until you can teach it.
Texas Instruments placement FAQs
Process & papers
What is the Texas Instruments placement process?
HirePro OA (common aptitude + up to two profile technicals) → 1-2 technical interviews → HR. Core analog/digital written tests are MCQ, not coding. Campus end-to-end often 1-3 weeks.
How many rounds are there in Texas Instruments interview?
Most fresher loops report 3 stages: OA, technical (sometimes two), HR. Reaching HR usually means technical is largely cleared.
Can I download Texas Instruments placement papers PDF?
Yes. Free TI placement papers PDF and 2024-2026 style practice are on this site. Start with the 2026 PDF or the archive.
What is the Texas Instruments online assessment exam pattern?
Common aptitude (~14-20 Q, ~20-30 min, negative marking) plus ~20 technical MCQs per profile (~30-45 min). IITG intern: 20+20, 30 min + 45 min per role, HirePro. Software variant: 20 apt + 10 tech, no coding.
Eligibility & offer
What is Texas Instruments eligibility criteria for freshers 2026?
Commonly 7.0 CGPA, 60% in 10th/12th, no active backlogs. ECE/EEE/E&I for Analog/Digital; CSE for Embedded. Your CDC mail overrides this page.
What is Texas Instruments salary for freshers in India?
Candidate-reported CTC often lands around ₹14-25 LPA (as of August 2026) for core Bengaluru freshers. The written offer is the only number that matters.
Which branches can apply to Texas Instruments?
Analog/Digital: ECE, EEE, Instrumentation. Embedded: those plus CSE (and MnC/Physics on some intern lists). Read the role list.
Prep & TI-specific
How to prepare for Texas Instruments placement?
Two profiles max. Aptitude accuracy. Analog RC/MOS, Digital FSM/timing, Embedded C/OS. Defend projects to component level. Details: preparation guide.
Can I attempt Analog and Digital together in the TI OA?
Yes on many campuses. Aptitude is common; each profile has its own timer. Cap is typically two technical sections.
Is there a coding round for analog roles?
Usually no in the written Analog/Digital test. Embedded/Software MCQs include C/DSA. Interviews for core profiles stay circuit- and project-heavy.
What programming languages are allowed in Texas Instruments?
C is the Embedded default. C++/Python appear. Digital cares about Verilog. Analog cares about circuits first.
Any pro tip for Texas Instruments placement preparation?
Do not guess on aptitude. Drill second-year fundamentals in tricky wrappers. Open your ADC or C project cold. That beats a high CGPA with shallow labs.
Where can I read real interview experiences?
Start with TI interview experience, then KGP FORESIGHT 2024/2025 Medium posts and GFG IITG intern notes.
Texas Instruments vs Qualcomm vs Intel for freshers?
TI: analog-heavy, profile-split HirePro, project interviews. Qualcomm: comms/SoC, more coding on some software tracks. Intel: stronger DSA OA, firmware/DV split. Prep circuits for TI analog/digital; add C/OS for TI embedded and Intel firmware.
What recent candidates reported
Full write-ups stay on interview experience.
What to steal this week
Steal: two-profile plan; no aptitude guessing; one project taught to component level; C endianness if Embedded.
Ignore: treating TI like a LeetCode company; sitting three profiles; “I’ll read Razavi the night before.”
If you only do three things: one timed aptitude with skip rules, one profile MCQ set, and a 20-minute project lecture to a friend.
IIT Kharagpur Analog, 2024 (Arpan Deb)
Sat Analog + Digital OA. Analog interview: RC without DEs, poles/zeros, current mirrors, SAR/Flash ADC details, then a long ADC-project grill (power, comparator, redundancy). Offered Analog before Digital interview. Takeaway: one excellent profile beats two mediocre ones.
Source: FORESIGHT 2024, Medium.
IIT Kharagpur Analog VLSI, 2025 (Satya Sai Kommana)
Written, one technical, HR (peers sometimes had two technicals). Role: Analog VLSI Engineer. CGPA 7.0. Core subjects over PORs. Takeaway: start analog problem sets early; analog is harder to self-check than digital.
Source: FORESIGHT 2025, Medium.
IIT Guwahati intern, HirePro + Webex
CPI 7.0. 20 apt + 20 per role. Shortlists by Analog/Digital/Embedded/Signal Processing. Digital interview on Cisco Webex with screen share; concept choice; ~1h15. Results next day.
Source: GFG TI internships on-campus.
Software on-campus (GFG)
Written 20 apt + 10 tech MCQs, no coding. Interview: endianness, cache coherence, aligned malloc. HR: Why TI?, free time. 2 of ~24 software shortlists selected. Takeaway: software at TI still feels systems-C, not web.
What selected vs rejected patterns look like
Helped: skip rules on aptitude; one project with numbers; honest “I sat Analog because of this lab.”
Hurt: guessing; claiming three profiles; cannot open the schematic; treating HR as the hard round.
More narratives: Texas Instruments interview experience.